1. Technical Field
The present invention relates to semiconductor devices and processing and more particularly to a structure and method for forming structures that reduce junction leakage.
2. Description of the Related Art
Junction leakage becomes a serious problem for low power technologies and particularly for technologies where devices are scaled beyond a 32 nm node. To control device short channel effects, dopant diffusion should be limited. This is done by reducing the thermal budget, which in turn results in incomplete removal of the defects generated by dopant ion implantation. Also, with very shallow junctions, the space between a silicide and junction becomes small, which results in excessive junction leakage.
Raised source drain structures are considered as a way to alleviate these problems. However, conventional raised source drain structure leads to excessive increases in the device parasitic capacitance. Depending on the integration scheme, disposable spacers might be needed, which make the process more complicated. In addition, there are concerns about junction leakage at an edge of the shallow trench isolation (STI). Usually a divot exists at the STI edge and if the junction is not deep enough at this point, silicide formation at the STI edge causes additional leakage.